DSPIC33
Product Features
Operating Conditions
3.0V to 3.6V
-40ºC to +125ºC, DC to 100 MHz
-40ºC to +150ºC, DC to 70 MHz
Up to 256 KBytes of Program Flash with ECC and Live Update (dual-partition Flash)
Up to 24 KBytes of Data SRAM with Memory Built in Self-Test (MBIST)
Modified Harvard architecture with 16-bit data and 24-bit instructions
Code efficient (C and Assembly) CPU architecture designed for real-time applications
16x 16-bit working registers
4 sets of interrupt context saving registers, including ACC and CPU status for fast interrupt handling
Single-cycle, mixed-sign 32-bit MUL
Fast 6-cycle hardware 32/16 and 16/16 DIV
Dual 40-bit fixed point Accumulators (ACC) for DSP operations
Single-cycle MAC/MPY with dual data fetch and result write-back
Zero overhead looping support
8 independent PWM pairs (16 total outputs) with up to 250ps resolution
Dead-time insertion for rising and falling edges and dead-time compensation support
Clock chopping for high-frequency operation
Fault and current limit inputs
Flexible trigger configuration for ADC triggering
3 12-bit 3.5 MSPS ADC Modules each with 2 dedicated SARs and 1 shared SAR cores (3 S&Hs)
12, 16, 19, 20 or 24 ADC input channels (depending on package)
4 digital comparators for reducing CPU overhead
4 oversampling filers up to 256x for increased resolution (up to 16-bits)
3 analog comparators (15ns) with dedicated 12-bit DACs with hardware slope compensation
Up to 3 op amps with internal connection to ADC Module
dsPIC33CK DSC Core
Advanced Analog Features